One of the difficulties in designing a memory circuit is optimizing the timing of the clock signals that enable various functions in the memory circuit. Inherent in any clock signal is the propagation delay from the circuit that transmits the clock signal to the circuit that receives it. When a clock signal is generated, it is generally for enabling some function, and more specifically, for enabling some other circuit that plays a role in the function which is being enabled. The clock signal is provided for timing purposes in order to optimize a delay that is required. One thing that has been done to assist in this timing is to program that delay. One of the characteristics of that approach is that there must be some features, such as fuses, which are programmed in order to implement such programmed delay. Such fuses require space on the integrated circuit. Also, the clock signal that is generated can be optimized for one circuit that it is enabling, but because of the differences in delay based upon location of the receiving circuitry, another circuit may be clocked at a less than optimum point in time. Some level of optimization is provided, but using fuses to program a delay does not solve all of the problems associated with optimum control of the delay. The fuses, however, do take up space so each programmable delay element not only requires additional space for itself, but more than one delay must be included. Thus, there is more circuitry required than just one global delay circuit. In addition to that, there is the fusible links or other mechanisms required to perform that programming.
In memory design the advantages of dynamic amplifiers are well known. The advantage of a dynamic amplifier over a static amplifier is primarily power savings. The advantage of a static amplifier is that it will amplify whatever signal is there, whenever it is there, and does not latch the data. So as soon as the data arrives, it will begin amplifying and if the data has to reverse itself or that the initial data has noise on it, there is no risk that the output will provide wrong data because it will not latch in a wrong direction. It will reverse itself if it begins in the wrong direction and will ultimately provide the correct data. In a dynamic amplifier, the data is latched as soon as the amplifier is enabled. If wrong or inadequate data is there at that time, it could latch in the wrong direction. So to take advantage of the low power aspect of a dynamic amplifier, it is very important that the timing of its being enabled be optimized. There is a speed penalty if it is enabled later than necessary. There is a reliability problem if it is enabled too soon. With proper timing, the speed may also be faster for a dynamic amplifier than for a static amplifier.
In a memory there are typically many subarrays that divide up the memory for improved efficiency in power consumption and in speed of accessing the data. There are long lines that carry data to and from the inputs into the memory cell locations. There are also clock signals that may spread throughout the entire chip. The distance from the initiation of those clocks to the circuit that receives those can vary greatly in distance and thus there can be inconsistent delays from when one circuit receives the clock from another. This problem applies to dynamic amplifiers because they require a clock in order to be enabled. Also, dynamic amplifiers are going to be subject to processing, power supply voltage, and other secondary effects that will effect how such amplifiers are clocked. Such secondary effects may include noise generated by other aspects of the integrated circuit and such noise may vary based on location within the integrated circuit. These types of variations create a difficulty for implementing dynamic amplifiers in a memory. Thus there is a need for a system for optimizing clocks whereby the circuitry which is receiving the clocks is receiving the clock at its proper time.